N64 Programming Manual Chapter 13

Tile Attributes

The RDP has a small on-chip memory for buffering up to eight tile descriptors at a time. A tile descriptor contains all the information for a texture tile including format; size; line; Tmem address; palette; mirror enable S, T; mask S, T; shift S, T; SL, TL; SH, TH; and clamp S, T.

Format
Format of texels in texture tile.

Table 1 Tile Format Encoding

Format Value Format

0 RGBA

1 YUV

2 CI

3 IA

4 I

Size
Size of texels in texture tile.

Table 2 Size of Texels in Texture Tile

Size Value Size of texel in bits

0 4

1 8

2 16

3 32

Line
Number of 64-bit words in one row of the tile. Dependent on tile row width as well as texel type/size. When tiles are loaded using the LoadTile command, the rows are padded to 64-bit boundaries. When LoadBlock is used to load a texture, it is assumed that the rows have already been padded. Line can also be used to control the stride through TMEM. By controlling Line, smaller tiles can be pieced together into one larger continuous tile.

Tmem Address
Tile offset (0-511) in Tmem (64-bit) words.

Palette
Palette number (0-15) of 4-bit Color Index (CI) textures. An 8-bit index into the high half of Tmem is formed by placing the palette number in the 4 MSBs and the 4-bit texel value in the 4 LSBs. The color in Tmem at this index becomes the color of the pixel. Therefore, for a 4-bit CI texture, you may select one of 16 palettes with each palette having up to 16 entries. Palettes can be loaded into Tmem using the LoadTLUT command or, optionally, the LoadBlock command.

Mirror Enable S,T
Enables mirroring of texture coordinates. When the bit indicated by the (Mask Value + 1) is 0 the coordinates are unchanged. When this bit is 1, however, the coordinates are inverted. Useful for symmetric patterns like trees, faces, etc. For example, a mask of 2 with mirror enabled would yield the following texture coordinates:

0,1,2,3,4,5,6,7,...Input coordinate
0,1,2,3,3,2,1,0,...Mirrored Coordinate

Mask S,T
Number of bits of tile coordinate to let through. For example, a mask of 1 indicates one bit of the texture coordinate should come through the mask, giving a pattern of 0,1,0,1... As another example, a mask value of 5 indicates that the texture should wrap every 32 texels, i.e., the lower 5 bits are passed through the mask. A mask value of 0 forces clamping the texture coordinates to be between (SL,TL),(SH,TH) inclusive. The mask value + 1 indicates the bit position that is looked at for mirroring. See discussion in Mirror Enable, above.

Shift S,T
Shift texture coordinates after perspective divide. Used in MIP maps and possibly for precision reasons (see the discussion of Detail texture later in this document). Also useful for combining two differently scaled textures.

Table 3 Shift Encoding

Shift Value Shift

0 no shift

1 >> 1

2 >> 2

3 >> 3

4 >> 4

5 >> 5

6 >> 6

7 >> 7

8 >> 8

9 >> 9

10 >> 10

11 << 5

12 << 4

13 << 3

14 << 2

15 << 1

SL,TL
When rendering, the starting texel column, row of tile in texture image space, 10.2 fixed point. Can be used to slide texture w.r.t. the primitive. When loading, the starting texel column, row within the DRAM texture image.

SH,TH
When rendering, the ending texel column, row of tile in texture image space, 10.2 fixed point. Used for clamping only. When loading, the ending texel column, row within the DRAM texture image.

Clamp S,T
Enable clamp during wrap or mirror. When not masking, Clamp S,T is ignored and clamping is implicitly enabled. This bit allows clamping the texture coordinates when the mask is non-zero. Useful when you want to mirror and then clamp like an airplane wing insignia. The border of the insignia would have an alpha of 0. For example, SH = 11, mask = 2, mirror = 1, clamp = 1:

0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,...Input Coordinate
0,1,2,3,3,2,1,0,0,1, 2, 3, 3, 3, 3, 3,...Mirrored/Clamped 
Coordinates

Shift Value	Shift
0	no shift
1	>> 1
2	>> 2
3	>> 3
4	>> 4
5	>> 5
6	>> 6
7	>> 7
8	>> 8
9	>> 9
10	>> 10
11	<< 5
12	<< 4
13	<< 3
14	<< 2
15	<< 1