Flushing the CPU Data Cache

The MIPS R4300 CPU transparently caches data accesses on a onboard data cache. Ordinarily this cache is of no concern to the application, but when an external agent such as the SP or DMA engine is involved, the application must be aware of the caching implications.

The data cache implements a “write back” replacement policy which means that data stores are held in the cache until the entire cache line is written back, usually due to a cache miss thatrequires the same cache line. The cache is not coherent with respect to physical memory and thus cache lines must be explicitly written back to memory prior to their use by another processor such as the SP.

Using the above example, the dynamic data can be written with a single procedure call as follows. It is expected that this will be done prior to the task list being executed by the SP.

              osWritebackDCache(dynamicp, sizeof(Dynamic_t));

Copyright © 1999 Nintendo of America Inc. All Rights Reserved Nintendo and N64 are registered trademarks of Nintendo Last Updated January, 1999