Texture Memory

Memory Organization
Because texturing requires a large amount of random accesses with consistent access time to texture memory, it is impractical to texture directly from DRAM. The approach taken by the Nintendo 64 system is to cache up to 4 KB of an image in an on-chip, high-speed texture memory called Tmem. All primitives are textured using the contents of Tmem. The basic sequence of events needed to texture a primitive is:

1. Load a texture tile into Tmem.

2. Describe attributes of the texture tile.

3. Render primitives that use this tile.

Tmem should indeed be considered a cache from the programmer’s point of view. Since each tile must be loaded from DRAM, it makes sense to render as many primitives as possible, using the current tile before loading the next one in order to conserve DRAM bandwidth.

Physically, Tmem is arranged as shown in the following figure. L0-3 are referred to as the low half of Tmem, H0-3 are referred to as the high half of Tmem.

Figure 13.8.1 Physical Tmem Diagram

For loading, Tmem is arranged logically, as shown in the following figure.

Figure 13.8.2 Tmem Loading

The following table shows the maximum tile sizes that can be stored in the 4KB Texture Memory. Images larger than this will be tiled.

Table 1 Maximum tile sizes in TMEM

Texel Type | Maximum Texel Count
4-bit (I, IA) | 8K
4-bit Color Index | 4K (plus 16 palettes)
8-bit (I, IA) | 4K
8-bit Color Index | 2K (plus 256-entry LUT)
16-bit RGBA | 2K
16-bit IA | 2K
16-bit YUV | 2K Y’s, 1K UV pairs
32-bit RGBA | 1K

Four-bit textures are stored in Tmem, as shown in the following figures.

Figure 13.8.3 Four-Bit Texel Layout in Tmem

Eight-bit textures are stored in Tmem, as shown in the following figure.

Figure 13.8.4 Eight-Bit Texel Layout in Tmem

Sixteen-bit textures (except YUV) are stored in Tmem, as shown in the following figure.

Figure 13.8.5 Sixteen-Bit Texel Layout in Tmem

Sixteen-bit YUV textures are stored in Tmem, as shown in Figure 15-14. Note that YUV texels must be loaded in pairs. In other words two Y’s at a time. Also note that if filtering is enabled, an additional UYVY pair must be loaded per row and SH set accordingly to allow proper filtering of the last UV texel per row.

Figure 13.8.6 YUV Texel Layout in Tmem

Thirty-two bit (RGBA) textures are stored in Tmem, as shown in the following figure.

Figure 13.8.7 Thirty-Two Bit RGBA Texel Layout in Tmem

For color index (CI) textures, the texture is stored in the lower half of Tmem, and the Texture/Color Look-Up Table (TLUT) is stored in the upper half of Tmem. For 4-bit CI textures, the texels (or indices) addressed in the lower half of Tmem have the 4-bit palette number for the tile prepended to create an 8-bit address into the upper half of Tmem. Since four texels are addressed simultaneously, there must be four (usually identical) TLUTs stored in the upper half of Tmem across the four banks.

For 4-bit CI textures, the palette effectively selects one of sixteen possible tables, each table having sixteen entries. Each table is aligned on 16-word boundaries. Note that there are two choices for the texel type that resides in the TLUT: 16-bit RGBA, or 16-bit IA. The type is selected using the gDPSetTextureLUT() command. This command also configures the Tmem as shown in the following figure. Because of this, CI textures cannot be combined with other texture types in two-cycle mode.

Figure 13.8.8 Tmem Organization for Eight-Bit Color Index Textures

Eight-bit CI textures do not use the palette number of the tile, since they address the whole 256 TLUT directly. It is possible to use the 8-bit mode for storing index textures that have between 16 and 256 entries.

For example, you could define a texture that had 40 entries, numbered 0-39, and load the TLUT into the upper half of Tmem (word 256). Further suppose that you had another texture with indices 40-69. You could load this texture’s 30 entry TLUT into Tmem, starting at word 296.

Assuming that both textures together fit into the lower half of Tmem (2 KB), these textures could be co-resident in Tmem. It is also possible to have CI textures co-resident with other non-CI textures. In the above example, you are using only the first 70 words of upper Tmem for TLUTs. You could use the remaining 186 words to store a 4-bit I texture, for example. Note that even though you can store CI and other types together in Tmem, you cannot access these types simultaneously in two-cycle mode, because the configuration of the Tmem for CI textures is controlled with a mode bit that must be updated using the gDPSetTextureLUT command, as mentioned previously.

Figure 13.8.9 Tmem Organization for Four-Bit CI textures Textures

Texel Formatting
In the RDP graphics pipeline, most operations are done on 8-bit-per-component RGBA pixels. After looking up the texels, the texture unit converts them into the 32-bit RGBA format. Table 2 describes how each type is converted. The format for beatified descriptions is [MSB:LSB] where MSB is the most significant bit and LSB is the least significant bit. Bit fields are grouped together in braces {} with the most significant field on the left and the least significant field on the right.

Table 2 Texel Output Formatting

Copyright © 1999 Nintendo of America Inc. All Rights Reserved Nintendo and N64 are registered trademarks of Nintendo Last Updated January, 1999