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Managing the Translation Lookaside Buffer
Although most applications will find the direct mapped KSEG0 address space of the CPU sufficient, it is possible to use the mapped address space by setting appropriate Translation Lookaside Buffer (TLB) entries.
Perhaps the biggest restriction with using the TLB is that individual entries operate only on relatively large, aligned memory regions (pages). Nevertheless, it may be helpful for memory protection or relocation of CPU addresses. In addition, TLBs can be used as yet another method to reconcile SP segment addresses with CPU addresses, since SP addresses fall within the range of the mapped CPU address space.
The translation lookaside buffer (TLB) of the R4300 has 32 entries, each of which maps two physical pages. The TLB is fully associative, which means each entry is essentially independent—the index number implies nothing about the mapping and any entry can hold any mapping. A number of page sizes are supported: 4 KB, 16 KB, 64 KB, 256 KB, 1MB, and 16MB. Each TLB entry may map a different page size. The following routines are used to manage the TLB:
Using the TLB requires some care. The following paragraphs describe some problem areas.
This function sets the contents of a single TLB entry to the given virtual address, even and odd physical address, page size, and address space identifier.
This function invalidates both the odd and even physical page mappings of a given TLB entry.
This function invalidates all mappings in the TLB. This should be done by the application prior to using the TLB.
This function sets the current address space identifier register.
osMapTLB(0, OS_PM_16K,(void *)0x0,0xa0000,-1,-1);
osMapTLB(1, OS_PM_4K, (void *)0x2000, 0xb000, -1, -1);
Another case involves different TLB entries, each of which map different pages of an odd/even pair. The following mappings, which individually map an even and an odd physical page, will create an overlap condition:
osMapTLB(0, OS_PM_4K, (void *)0x2000,0xa000,-1, -1); osMapTLB(1, OS_PM_4K, (void *)0x2000,-1,0xb000, -1);
Instead, the application should set a single entry with both mappings:
osMapTLB(1, OS_PM_4K, (void *)0x2000, 0xa000, 0xb000, -1);
This implies that if one intends to map SP segment addresses via the TLB, the SP segment must be loaded at a page-aligned address.
If you cannot use the same virtual address, the mappings should all be the same color, where the “color” is defined as bits [14..6] of the instruction address (for instruction fetches) or bits [15 ..5] of the data address (for data accesses).
Finally, no support is provided for handling and recovering from TLB misses. A TLB miss is an unrecoverable fault to the Nintendo 64 system.
More information about these topics can be found in the MIPS R4300 documentation.
Copyright © 1999 Nintendo of America Inc. All Rights Reserved Nintendo and N64 are registered trademarks of Nintendo Last Updated January, 1999 |