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osInvalDCache
Format#include <ultra64.h>
void osInvalDCache(void *vaddr, s32 nbytes);
What This Functions Does
It invalidates CPU data cache lines.
The MIPS R4300 CPU implements an 8-kilobyte direct-mapped data cache with a line size of 16 bytes. The cache is not coherent with respect to physical memory and thus cache lines must be explicitly invalidated to ensure that stale data is not used when more recent data exists in physical memory. The osInvalDCache call invalidates all data cache lines that contain the region [vaddr, vaddr + nbytes). The given address vaddr must be a CPU virtual address, either direct mapped or mapped by way of the CPU translation lookaside buffer (TLB). If vaddr is not aligned to the a cache line boundary, and nbytes is not a multiple of the cache line size, a slightly larger region may be invalidated.
This routine is most frequently used in the situation where newer program data is to be copied to physical memory from a direct memory access (DMA) device at address locations that have been previously read or written to by the CPU. In this case, the cached data is out of date with respect to physical memory, and thus cache lines associated with these addresses must be invalidated prior to accessing these data locations.
See Also
osMapTLB
osInvalICache
osWritebackDCache
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Nintendo® Confidential Warning: all information in this document is confidential and covered by a non-disclosure agreement. You are responsible for keeping this information confidential and protected. Nintendo will vigorously enforce this responsibility. Copyright © 1998 Nintendo of America Inc. All rights reserved Nintendo and N64 are registered trademarks of Nintendo Last updated January 1998 |