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osInvalICache
Format#include <ultra64.h>
void osInvalICache(void *vaddr, s32 nbytes);
What This Function Does
It invalidates CPU instruction cache lines.
The MIPS R4300 CPU implements a 16-kilobyte direct-mapped instruction cache with a line size of 32 bytes. The cache is not coherent with respect to physical memory or the data cache and thus cache lines must be explicitly invalidated to ensure that stale instructions are not used when more recent data exists in physical memory. The osInvalICache call invalidates all instruction cache lines that contain the region [vaddr, vaddr + nbytes). The given address vaddr must be a CPU virtual address, either direct mapped or mapped by with of the CPU translation lookaside buffer (TLB). If vaddr is not aligned to the a cache line boundary, and nbytes is not a multiple of the cache line size, a slightly larger region may be invalidated. For all practical purposes, this is harmless.
It is necessary to invalidate the instruction cache when previously executed instructions are out of date with respect to physical memory. The situation most frequently occurs when a new code is copied into physical memory through a direct memory access (DMA) device. If so, addresses associated with program text must be invalidated prior to executing the code at these addresses.
See Also
osMapTLB
osInvalDCache
osWritebackDCache
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Nintendo® Confidential Warning: all information in this document is confidential and covered by a non-disclosure agreement. You are responsible for keeping this information confidential and protected. Nintendo will vigorously enforce this responsibility. Copyright © 1998 Nintendo of America Inc. All rights reserved Nintendo and N64 are registered trademarks of Nintendo Last updated January 1998 |